In typical multilayer semiconductor device the uppermost layers which are electrically interconnected with underlying layers by way of, for example, vias, additionally include bonding pads for forming electrical connection with the semiconductor device (chip) surface to a package which contains the chip. The bonding pads are typically formed in an array on the individual die or chips likewise forming an array on the semiconductor wafer surface.
In forming wire bonding pads on the chip upper surface for subsequent wire bonding from the chip to a package frame by various techniques, a conductive area, for example copper, is covered by a series of passivation layers in which an opening is subsequently anisotropically etched to form closed communication with the copper conductive area and filled with another metal, for example aluminum or an aluminum/copper alloy.
For example, referring to FIG. 1A is shown a portion of a multilevel semiconductor device including a stage in formation of a bonding pad including conductive area 11A formed in dielectric insulating layer 11B having an overlying silicon oxynitride or silicon nitride etching stop liner 12. Overlying the etching stop liner 12 is a passivating dielectric insulating layer 14 typically formed of undoped silica glass (USG) with an overlying layer of silicon nitride 16. A photoresist layer 18A is deposited and photolithographically patterned to form an opening 18B for anisotropically etching a bonding pad opening.
Referring to FIG. 1B, the bonding pad opening 20A is anisotropically etched through the silicon nitride layer 16 and the USG layer 14 to form closed communication with the etching stop liner 12. Referring to FIG. 1C, the photoresist layer 18A is then removed by a plasma ashing process and another anisotropic etching step is carried out to etch through the etching stop liner 12 to reveal the underlying conductive 11A to complete the formation of bonding pad opening 20A. Referring to FIG. 1D, the bonding pad opening is filled with an aluminum or aluminum copper alloy to form wire bonding pad 20B.
One problem with the prior art method of formation of wire bonding pads is that adhesion of the metal bonding pad, for example aluminum or aluminum/copper alloy, to the passivation layers is poor. As a result, during wire bonding operations including for example, thermocompression or thermosonic wire bonding, a downward compressive force is exerted causing some deformation of the bonding pad as well an upward force on removing the wire bonding stylus. The bonding pad is further subjected to a variety of other stresses during the packaging process including stresses caused by heating and cooling together with thermal coefficients of expansion mismatches between the various materials. Frequently, the exposure of the wire bonding pad to repeated stresses causes peeling of the bonding pad due to poor adhesion of the wire bonding pad the passivation layers and to the underlying conductive area, for example, copper. As a result, chip yields are reduced leading to costly re-working procedures.
There is therefore a need in the semiconductor processing art to develop a method whereby metal filled semiconductor features are formed to improve structural stability to avoid or prevent peeling during subsequent processing steps.
It is therefore an object of the invention to provide a method whereby metal filled semiconductor features are formed to improve structural stability to avoid or prevent peeling during subsequent processing steps while overcoming other deficiencies and shortcomings of the prior art.